The present invention relates to a semiconductor device and an interconnect substrate and it particularly relates to a technique which is effective when applied to a semiconductor device capable of high speed communication.
In recent years, a communication speed in network communication has been increased more and a signal transmission speed exceeding 10 Gbps has been used generally in network equipment. Accordingly, signal reflection by parasitic capacitance of interface buffers (I/O devices) of communication semiconductor devices (LSI: large scale integrated circuits) mounted on the network equipment deteriorates signal quality, which imposes a significant problem. This is considered to be attributable to that the admittance of the parasitic capacitance increases more as the operation frequency of the I/O device is higher, which greatly lowers the input/output impedance of the I/O device to result impedance mismatching between the I/O device and the signal transmission line. For example, it is assumed a case that an I/O device having a parasitic capacitance on the output side and an I/O device having a parasitic capacitance on the input side are connected by way of a signal transmission line having a characteristic impedance of 50Ω. In this case, even when each of the input resistance of the I/O device on the input side and the output resistance of the I/O device on the output side is defined theoretically at 50Ω, the admittance of the parasitic capacitance of the I/O device on the input side and that on the output side increase as the frequency of the transmitted signal is higher, which lowers the input impedance of the I/O device on the input side and the output impedance of the I/O device on the output side. For example, when the parasitic capacitance of the I/O device on the input side and that on the output side is 1 pF, the input/output impedance of each of the I/O devices is about 45Ω at 1.25 GHz, about 25Ω at 3.2 GHz (corresponding to 6.4 Gbps), and about 14Ω at 5.0 GHz (corresponding 10 Gbps). Lowering of the input/output impedance of the I/O device causes remarkable impedance mismatching between the signal transmission line and the I/O device to greatly distort the signal waveform.
For mitigating the effect of the parasitic capacitance of the I/O device, it has been known so far a technique of forming an impedance matching circuit on a semiconductor chip in which the I/O device is formed, or burying an inductor (L), a capacitor (C), and a resistor (R) in an interconnect substrate of a semiconductor substrate (packaging substrate) for mounting the semiconductor chip, thereby compensating the impedance mismatching. In addition, an existent technique of decreasing the distortion of the waveform caused by impedance mismatching is disclosed as a relevant technique, for example, in Japanese Patent Laid-Open Nos. 2006-49645 and 2012-209340. Japanese Unexamined Patent Application Publication No. 2006-49645 discloses a configuration of disposing plural through holes for grounding interconnect around a signal through hole in a printed substrate. Japanese Unexamined Patent Application Publication No. 2012-209340 discloses a configuration of a signal transmission line which is formed including through via holes (through holes) for connecting an outer layer pattern and an inner layer pattern of a multilayer substrate where buried via holes are disposed at a position adjacent to the through via hole with an insulator being put between them.